Experienced Senior ASIC / RFIC Designer
Analog / mixed signal / RF IC design
Project planning / management
Design of communication systems, system analysis, RF/transceiver budget
17 years of experience with ASICs, simulation, circuits, RF, system analysis
Responsibility, sense of planning and management, time scheduling
Experienced in a lab
Analog / mixed signal / RF IC design
Projektplanlægning og -styring
Design af kommunikationssystemer, system analyse, RF/transceiver budget
17 års erfaring med ASICs, simulering, kredsløb, RF, system analyse
Ansvarlig, flair for planlægning, tidsplaner, projektplanlægning og -ledelse
Taler adskillige sprog
Konstruktion von Systemen im Bereich Analoges / mixed Signal, RF ICs
Planung und Verwaltung von Projekten
Konstruktion und Analyse von Kommunikationssystemen
17 Jahre Erfahrung im Bereiche von ASICs, Simulation, Stromkreise, RF, Systemanalyse
Verantwortlich, Kompetenz für Projektplanung
Spreche mehrere Sprachen
Design de sistemas de analog / mixed signal, RF ICs
Planejamento e gerenciamento de projetos
Construção e análise de sistemas de comunicação
17 anos de experiência de ASICs, simulação, circuitos, RF, análise de sistemas
Responsável, competência de planejamento de projetos
Poliglota (falo português)
C. V. For Henning Petersen
Bachelor of Engineering, graduated from Københavns Teknikum in 1993. Started playing with electronics at the age of 12, computer programming at the age of 14. Now Senior Asic Designer, RF/analog/mixed. RF system budgets – system architect.
Work style: Thorough, systematic, determined, good planner and administrator. Skilled in writing clear, thorough documentation. Easy learner. Keeps track of top overview and the details.
Besides design, some of my forces are planning, documentation, clear communication and administration. These are key parameters in achieving success with the system integration, e.g. assuring that the blocks together will make the entire chip work as thought. This is especially important in cross site projects, and of course in the work with external customers and vendors.
I have a broad knowledge of the many aspects of engineering, administrative methods and business areas, gained through 17 years of experience: as employee at the university, in large international companies, and in a small startup company, financed by investors and project sales; within both chip design and discrete electronics design.
I have lived abroad for a period, and throughout my career I have worked with customers/vendors/sites in Denmark, Japan, Korea, Sweden, Finland, Norway, France, Germany, US, UK and Israel. My current residence is Copenhagen, Denmark.
As a person, I am regarded as a friendly colleague, always ready to help with job tasks or elsewhere.
Engineer since 1993:
2010 - present: Analog ASIC designer at ICEpower Bang & Olufsen
2001 - 2010: Senior RF/analog/mixed signal Asic designer in Polaric/Silicide
2000 - 2001: Motorola Copenhagen - designer on Tetra mobile radio project
1995 - 2000: RF/analog Asic designer in Nokia Mobile Phones Copenhagen
1993 - 1995: Technical University of Denmark (DTU), design on Ørsted satellite project
1993: Final thesis at DTU: Magnetic vacuum control system generating zero Tesla field
IC design expertise and circuits:
PLL, high performance opamp design, class D high performance audio amplifier design, LNA, IQ RX+TX mixers, PA, active & passive filters, LF+HF amps and buffers, oscillator, bandgap reference, other bias circuits, logic gate design, DA convertor, regulation systems, RX & TX system budgets, 2+4 dividers/prescalers, coherent & noncoherent demodulators, power on reset, RSSI circuit, AGC/VGA, symbol+clock regen, ultra low power / voltage, robust design over voltage & temperature, full custom layout of circuits, modelling & verification of semiconductor and res/cap/inductors on-chip & discrete, analog/power/IO pads, top level simulation, production test & mass production, design for test, NFC, stripline/microstrip design, class A/B/D/E/F amplifiers.
System design and signal processing:
System analysis + design for modulations OFDM/MSK/DSSS/other. Viterbi decoder
Detailed feasibility study and RF system budget on high performance LNA chain
Detailed feasibility study & system design for RF+analog+baseband of ZigBee chip
Design of simulation software for full RX+TX system for 802.11a/b/g+Hiperlan2 stds. Worked with Near Field Communication (NFC) systems and chip design
IC fab processes:
Bipolar, CMOS, BiCMOS, SOI-FD (CMOS - Silicon On Insulator - Fully Depleted). Also discrete devices of LDMOS and GaN
Group leader (chief) for 5 IC-designers in Nokia. Project planning and management. Experienced in setting realistic time schedules.
Documented several feasibility studies for external customers. Writes unambiguous documentation, doesn't leave loose ends in communication with partners and colleagues. Experienced in cross-cultural communication, worked with customers/vendors from Finland, UK, US, France, Germany, Scandinavia, Japan, Israel, Korea.
Laboratory and measurements:
Lab work in DC - 4 GHz frequency range, matching, network/spectrum/FFT analysers, RF/function generators, temperature+voltage automated characterisation. Nokia: chips for million+ products: GSM1800/1900 - PDC1500, direct conversion triple band IC in 350 million pcs.
Super user in analog / mixed signal / system design simulators
Aplac, Spice, HP-ADS, Layed, Eagle, Mentor IC Station/Design Architect, Eldo, Cadence PSPICE/OrCAD. Linux sysadmin, HPUX, Perl/Pascal/C/Tcl-Tk/shell scripting, HP-VEE, Labview, assembler code.
Danish, English, German, Portuguese, Swedish, Norwegian
Worked with patent applications, investigating competitor patents etc.
Elaborating on the CV
Developed and worked with a very broad range of analog/mixed signal circuits, many of them with tough specs. To mention a few: high gain ultra low power wakeup detector, opamps (normal or input/output rail-to-rail), high performance low noise highly linear opamps, bias and bandgaps, active high order filters, regulation systems, chip design for Hifi audio. Worked with Mentor Graphics programs like Design Architect, Eldo, IC Station, and the related DRC and LVS programs. APLAC super user. PSpice advanced level.
Low noise design:
Developed low noise designs in both LF (pre amplifiers, sensitive bias circuits) and RF (LNA, RX mixers) frequency ranges. Theoretical insight in the theory behind noise, thermical as well as 1/f noise. Familiar with noise calculations on device and circuit level, and also through spreadsheet noise budgetting. Knowledge of noise coupling from noisy blocks (through substrate/package) and the techniques to reduce the coupling and the impact.
Low power design:
Developed several circuits in μA-range, down to 1.2 Volts. Circuits were used in hearing aids and RTTT circuits (traffic control units, like for example BroBizz). I know how to combine low noise and low power designs by having clear overview of the system budget, meaning that the necessary power will be used in the block(s) where the benefit is maximized.
Low cost design:
Worked in the mobile phone business, and on an RTTT project. In both the mobile and the RTTT business, cost is very important. As such, I have been involved in the tradeoffs of chip area and package choice, as well as the cost of production test time, for example by cutting down the test time to include only the necessary tests, while ensuring only working devices to pass the tests.
Developed and worked with a very broad range of RF circuits, among these LNA's, RX/TX mixers, direct conversion and heterodyne receivers/transmitters, PLL's and VCO's, PA's, AGC/VGA's, RSSI. Also worked with system design; I have planned an entire ZigBee receiver where I had full liberty to select the receiver chain architecture, demodulation principle, and the interface to, and the system design of the digital baseband.
Switched amplifiers/power stages:
Designed class D nmos/pmos 0,35μm 250 mW output driver stages (100MHz-2GHz), and their prestage drivers, these were verified/tested on silicon. Designed discrete class F power amplifiers at frequencies 100/200/945 MHz, with semiconductors of the types LDMOS and GaN. Verified to work. These designs were thoroughly simulated, while acquiring theoretical and practical knowledge. Worked extensively with class F amplifier technology. Designed microstrip boards especially for switched amplifiers. Presently working with high end class D audio amplifiers.
Circuit design in general:
Please see the extensive list of blocks included in the general CV above. These designs have involved noise analysis, stability analysis, analysis over temperature, supply voltage, and statistical analysis (Monte Carlo) to determine and improve robustness. Analysis has been performed as DC, AC, steady state and transient analysis, as well as mixed system/analog analysis.
All chip designs have been targetted for mass production. In Nokia, the design teams did the chip design from specification to handling production. I participated in this process all along, and is used to the concept of designing for test, specifying test plans and making robust designs through Monte Carlo simulations and other techniques. My first chip project in Nokia shipped millions of chips, another shipped 350 millions, and I understand the importance of designing fault free circuits when designing for multi million production, and know the techniques used.
Process and modelling experience:
AMS, Infineon, Magna Chip, FD-SOI (from a large Japanese foundry, developing a fully depleted silicon on insulator process) as well as other processes not to be disclosed. Extensive insight and experience with various models (BJT/CMOS/HBT/SOI-CMOS/LDMOS), including verification and correcting errors/improving models. Insight in chip fabrication, mask stages, packaging, ESD-protection and requirements.
At both Nokia and Silicide, I did the layout personally including pad ring, interconnecting, and block layouts. Also running DRC and LVS. Knowledge of the parasithic phenomenons that limit the designs, knowledge of how to modify the simulation profiles to reflect parasithic limitations, found by parasithic extraction and by estimating unknown parasithics. Knowledge of coupling through substrate and what to do. Experience within the area of package modelling/parasithics. Done layout in IC Station and Catena Layed.
Simulation and design experience:
My major force is working with simulators, analog/mixed signal and discrete time system simulators, like Aplac (nowadays part of the AWR simulator suite, HP-ADS, Eldo (Spice), PSpice. I have designed reference code for the WLAN (802.11a/b/g) and Hiperlan 2 system simulators in a commercially available simulator.
Testing and lab experience:
Extensive lab experience in the range DC - 4 GHz, oscilloscope, fft, network, spectrum analyzer, DC current/voltage measuring. Experience with automated measurement setups and processing the data. Knows how to use a soldering iron, experienced in RF matching; I know my Smith charts.
PCB and microstrip design:
Supervised many PCB designs, low/high power, low/high frequency. I have designed microstrip boards, Duroid/FR4.
Project management, project specification:
I have conducted and managed many feasibility studies, working with French, Danish and Japanese customers. I had responsibility for a 5 person group of IC designers in Nokia.
Worked with scripting, automated/batch simulating, data processing from statistical/batch simulation setups. Knowledge to a broad range of EDA software like ELDO, HP-ADS, APLAC, Mentor Graphics suite, Layed, PSpice Linux power user. Have worked with remote access and management like backup, setup of home office running through command line and graphical interface (X11)
© 2017 Copyright